1. Field of the Invention
This invention relates generally to the manufacture of integrated circuits, and more particularly to the formation of horizontal and vertical scribe lines on an integrated circuit wafer which divide the wafer surface into a number of integrated circuit die areas.
2. Description of the Related Art
Integrated circuits are formed on semiconductor wafers typically made from silicon or gallium arsenide. Most often, the semiconductor wafer is made from silicon. These wafers are substantially round, but often include one or more "flats" or notches along their perimeters for the purposes of alignment during the integrated circuit fabrication process. The diameters of these wafers are continuously increasing, with four, six and eight inch diameter silicon wafers being common at the present time.
Since a single integrated circuit-die is often no more than 1 cm.sup.2, a great many integrated circuit die can be formed on a single semiconductor wafer. After the semiconductor wafer has been processed to form a number of integrated circuit die on its surface, the wafer is cut along "scribe lines" to separate the integrated circuit die for subsequent packaging and use.
FIG. 1 illustrates a processed semiconductor wafer 10 in accordance with the prior art. FIG. 1a is an enlarged, cross-sectional view of the portion of FIG. 1 encircled by the line 1a. As seen in FIGS. 1 and 1a, the processed semiconductor wafer 10 includes a number of integrated circuit die 12 which are separated by horizontal scribe lines 14 and vertical scribe lines 16. The horizontal scribe lines 14 are evenly spaced and parallel to each other. Likewise, the vertical scribe lines 16 are evenly spaced and parallel to each other. The horizontal scribe lines 14 and the vertical scribe lines 16 intersect at substantially right angles. After the wafer 10 has been processed such that functional die 12 are present on the surface of the wafer, the wafer 10 is cut into individual integrated circuit die by cutting along the scribe lines 14 and 16. This cutting process, as it is well known to those skilled in the art, typically includes a sawing process or a laser cutting process.
As best seen in FIG. 1a, the processed semiconductor wafer 10 includes a substrate 18 and the number of layers 20 formed over the substrate 18. A vertical scribe line 16a can be seen formed in the layers 20. It should be noted that a "scribe line" is often an elongated slot, groove, or opening provided through layers formed over a substrate, rather than a physical structure. In some instances the scribe line is filled with a material such as silicon dioxide, thereby creating a scribe line having a physical structure. Alternatively, the scribe line might be an elongated raised area or "mesa" bounded on one or both sides by openings.
There may be as few as two or three layers 20, but often there will be eight or ten or even more layers 20 formed over the substrate 18. As it is well known to those skilled in the art, these layers 20 typically alternate between conductive type layers and insulating type layers. A particular layer can include several sub-layers, i.e. a conducting layer can comprise several conducting sub-layers, such as an aluminum layer over a titanium-tungsten alloy layer, and insulating type layers can comprise several sub-layers such as a plasma enhanced chemical vapor deposition (PECVD) layer, a spin-on-glass (SOG) layer, or other layer over an oxide layer, etc.
Practically speaking, the scribe lines such as scribe line 16a must be created concurrently during the formation of each of the layers 20. This is because a scribe line (such as scribe line 16a) is formed by an etching process which sequentially etches openings into the various layers. Since the various layers 20 of the processed wafer 10 are of different types and have different etching characteristics, the openings defining a scribe line 16a are preferably etched layer-by-layer as the layers are deposited. The scribe lines, such as scribe line 16a, may, as a last step, be filled with an oxide (not shown) or other insulation material to inhibit chipping and contamination of the scribe line area. Alternatively, mesa type scribe lines can be formed.
As used in the art, the term "opening" is be construed differently from the term "feature." Features, as the term is used in the art, can be positive (such as a mesa) or negative (such as a groove or slot). Some scribe lines of the prior art are elongated mesas (i.e. positive features), while other scribe lines of the prior art are elongated openings (i.e. negative features). Therefore, openings can comprise a scribe line, or these openings can be formed on both sides of a mesa which comprises a scribe line.
The dimensions of a scribe line, such as scribe line 16a, can vary considerably. For example, the width w of scribe line 16a is often in the range of 100-200 microns. The height H of the scribe line 16a may be 1.5-3 microns high. These dimensions are dependent on the design technology used by the integrated circuit designer.
It should be noted that the vertical and horizontal scales of FIG. 1a, and the vertical and horizontal scales of the remaining figures, are not the same in the horizontal and vertical directions. In the figures, the scale in the horizontal direction has been shrunk as much as two orders of magnitude relative to the scale in the vertical direction. These different scales are necessitated if both sidewalls of a scribe line are to be shown simultaneously without shrinking the height of the layers 20 excessively.
As the feature size of integrated circuits decreases, they become more susceptible to contamination. Contamination from scribe line artifacts has recently become a concern. The formation of scribe line artifact will be discussed with reference to FIGS. 2a and 2b.
In FIG. 2a, a number of layers 20' are formed over a semiconductor substrate 18'. A layer 22 is conformably deposited over the layers 22 and within a scribe line 24. Next, a mask 26 (typically comprising patterned photoresist) is formed over the layer 22 and exposed areas of the layer 22 are etched away. The etching is usually accomplished by an ansiotropic process such as a plasma etch process.
Unfortunately, as seen in FIG. 2b, the etching process is not always successful at removing all the materials within a scribe line 24. More particularly, "artifacts" 28 are often retained at the intersection between the base 30 and the sidewalls 32a and 32b of the scribe line 24. These artifacts 28 are not particularly damaging unless they become dislodged as indicated at 28' and land on an active portion of an integrated circuit die 12. For example, if the artifact 28' is conductive, it can short-out conductive features of an integrated circuit die. However, even if the artifact 28' comprises an insulating type material, it can cover or shadow a crucial portion of an integrated circuit die during the formation of the die, thereby destroying its functionality. These artifacts 28, which are intrinsically formed because the layer 22 is much thicker vertically next to the sidewalls 32a and 32b than it is on the base of the scribe line, have become a substantial source of integrated circuit contamination, and can greatly reduce the yield of functioning die 12 on a processed wafer 10.
Another problem encountered in the prior art is that of spin-on-material (SOM), such as photoresist or spin-on-glass (SOG). In FIG. 3, a number of layers 20" are formed over substrate 18" so as to provide a scribe line 34, and SOM layer 36 formed over the surface of the layers 20" by a liquid spinning process which tends to move the SOM material of layer 36 in a direction indicated by an arrow 38. This can cause a "pile-up" in an area 40 of the layer 36 and reduce the thickness in an area 42 of the layer 36. This is due to the impingement of the liquid SOM material 36 against a vertical sidewall 44 the scribe line. A thinner area 42 can be problematic because it is possible that there will be insufficient coverage on all portions of the wafer. The thickened portion 40 reduces the planarity of the semiconductor wafer 10, thereby making it more difficult to process subsequent layers formed over the SOM layer 36.
Another scribe line related problem is illustrated in FIG. 4. The illustrated problem is referred to as "trap." In a trap, a number of layers 20'" are formed over a substrate 18'". A scribe line 46 is deemed in the layers 20'". Sometimes, due to a misalignment of the masks used to pattern the layers, or due to undercutting by an etching process, or due to other factors, the sidewalls 48a and 48b of the scribe line are not entirely vertical. This can allow particles, such as particles 50a and 50b to become trapped by the sidewalls 48a and 48b, respectively, of the scribe line 46. These "particles", as the term is used by those skilled in the art, typically refer to airborne, liquid carried, or other foreign origin particles that were never a part of the wafer or any of its layers. As used herein, the term "particle" also include "debris", which is used by those skilled in the art to refer to matter that was once part of the wafer or one of the layers and which was subsequently dislodged as a separate bit of matter. Debris, for example, can comprise sidewall polymers from plasma etching or residual filaments from a deposited film.
If the particles 50a or 50b do not move, the trapping of the particles is not particularly problematical. However, the particles 50a or 50b become dislodged during the processing of the semiconductor wafer 10, they can contaminate one of the integrated circuit dies 12. Therefore, the "trap" problem is another source of potential contamination derived from the scribe line structure of the prior art.
Also, as seen in FIG. 4, the bottom of the scribe line 46 can form a "trench" 51. As is well known to those skilled in the art, this trenching occurs due to over-etching of one or more layers. Trenching is generally considered to be undesirable because it reduces the planarity of the substrate.